A register file is an array of processor registers (memory cells, bit cells) in a central processing unit (CPU). Modern integrated circuit-based register files may be implemented by way of fast static random access memories (SRAMs) with multiple ports having dedicated read and write ports. The memory cells may operate by discharging read and write bitlines to ground level during read and write operations respectively. The read and write bitlines may be precharged to a voltage source (Vcc) level after every operation and may be maintained at Vcc even in IDLE mode. Maintaining bitlines at Vcc level results in the register file suffering high leakage current. Discharging and precharging bitlines in full-swing to perform read/write operations requires high active power for the register file.
FIG. 1 illustrates an example memory cell 100 (e.g., 8 transistor memory cell). The memory cell 100 includes first and second transistors 110, 120 coupled together in series and third and fourth transistors 130, 140 coupled in series. Both series stacks are coupled between ground and Vcc and are cross coupled to one another (gate to source/drain connection). The first and third transistors 110, 130 may be positive channel transistors (e.g., PMOS) while the second and fourth transistors 120, 140 may be negative channel transistors (e.g., NMOS). The memory cell 100 also includes a fifth and sixth transistor 150, 160 coupled to the gates of the first series stack 110/120 and the second series stack 130/140 respectively. The fifth and sixth transistors 150, 160 are coupled to write wordline (gates) and write or writebar bitlines respectively. The transistors 150, 160 act as pass gates for writing data to the memory cell 100. When the memory cell is not in write mode (idle or read mode) the bitlines are tied high (Vcc). When the memory cell 100 is in write mode the write wordline is activated (set high) and the appropriate bitline (write or writebar) is discharged (set low) to write the appropriate bit to the memory cell 100.
The memory cell 100 further included seventh and eight transistors 170, 180 coupled together in series. The transistor 170 is coupled to read wordline and read bitline. When the memory cell 100 is not in read mode (idle or write mode) the read bitline is tied high. When the memory cell 100 is in read mode the read wordline is activated (set high) and the read bitline is discharged (set low) so that the data can be read from the memory cell 100.